VLSI

VLSI COURSE CONTENT

VECTOR Institute’s Program in VLSI Technologies revolves around ASIC, and includes the following study components.

ASIC / FPGA DESIGN

1. ASIC / FPGA Design Fundamentals
2. Advanced Digital Design

CMOS

1. MOS Fundamentals and Characterization
2. NMOS/PMOS/CMOS Technologies
3. Fabrication Principles
4. Different Styles of Fabrication for NMOS/PMOS/CMOS
5. Design with CMOS Gates
6. Characterization of CMOS Circuits
7. Scaling Effects
8. Sub-Micron Designs
9. Parasitic Extraction and Calculations
10. Subsystem Design
11. Layout Representation for CMOS Circuits
12. Design Exercise using CMOS
13. Introduction of IC Design
14. Different Methodologies for IC Design
15. Fabrication Flows and Fundamentals

VHDL

1. VHDL Overview and Concepts
2. Levels of Abstraction
3. Entity, Architecture
4. Data Types and declaration
5. Enumerated Data Types
6. Fabrication Principles
7. Relational, Logical, Arithmetic Operators
8. Signal and Variables, Constants
9. Process Statement
10. Concurrent Statements
11. When-else, With-select
12. Sequential Statement
13. If-then-else, Case
14. Slicing and Concatenation
15. Loop Statements
16. Delta Delay Concept
17. Arrays, Memory Modeling, FSM
18. Writing Procedures
19. Writing Functions
20. Behavioral / RTL Coding
21. Operator Overloading
22. Structural Coding
23. Component declarations and installations
24. Generate Statement
25. Configuration Block
26. Libraries, Standard packages
27. Local and Global Declarations
28. Package, Package body
29. Writing Test Benches
30. Assertion based verification
31. Files read and write operations
32. Code for complex FPGA and ASICs
33. Generics and Generic maps

VERILOG

• Language introduction
• Levels of abstraction
• Module, Ports types and declarations
• Registers and nets, Arrays
• Identifiers, Parameters
• Relational, Arithmetic, Logical, Bit-wise shift Operators
• Writing expressions
• Behavioral Modeling
• Structural Coding
• Continuous Assignments
• Procedural Statements
• Always, Initial Blocks, begin ebd, fork join
• Blocking and Non-blocking statements
• Operation Control Statements
• If, case
• Loops: while, for-loop, for-each, repeat
• Combination and sequential circuit designs
• Memory modeling,, state machines
• CMOS gate modeling
• Writing Tasks
• Writing Functions
• Compiler directives
• Conditional Compilation
• System Tasks
• Gate level primitives
• User defined primitives
• Delays, Specify block
• Testbenchs, modeling, timing checks
• Assertion based verification
• Code for synthesis
• Advanced topics
• Writing reusable code

System Verilog

• Introduction to System Verilog
• System Verilog Declaration spaces
• System Verilog Literal Values and Built-in Data Types
• System Verilog User-Defined and Enumerated Types
• System Verilog Arrays, Structures and Unions
• System Verilog Procedural Blocks, Tasks and Function
• System Verilog Procedural Statements
• Modelling Finite State Machines with System Verilog
• System Verilog Design Hierarchy
• System Verilog Interfaces
• Behavioral and Transaction Level Modelling

FPGA Flow

• Re-configurable Devices, FPGA’s/CPLD’s
• Architectures of XILINX, ALTERA Devices
• Designing with FPGAs
• FPGA’s and its Design Flows
• Architecture based coding
• Efficient resource utilization
• Constrains based synthesis
• False paths and multi cycle paths
• UCF file creation
• Timing analysis/Floor Planning
• Place and route/RPM
• Back annotation, Gate level simulation, SDF Format
• DSP on FPGA
• Writing Scripts
• Hands on experience with industry Standard Tools

ASIC Flow

Projects: As a part of course 2 mini projects and 1 major project

• EDA Tools / CAD Flow for IC Design
• Simulation/Synthesis using ASIC libraries
• Clock Tree Synthesis
• False paths / Multi cycle paths / Critical paths
• Design for Testability (DFT)
• Scan Insertion / Types of Scan
• Fault Models
• Logic BIST, Memory BIST, ATGP, Boundary Scan
• Pattern Compression
• Scan Diagnostics
• Layout Design
• Placing and Routing
• LVS/DRC/OPC/Physical verification
• Diagnosis, DFM, Yield Analysis
• SOC Design and Trade-offs
• Future Trends and challenges
• ASIC Case Studies

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